PXN20RM Datasheet, PDF (807/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
• A Buffer Done interrupt is generated (CSCRn[STS[2]] set) when the last quadlet from the last
packet (in the Current Buffer) has been successfully transmitted. (See Note 6 in Figure 27-19).
Single-packet buffering of asynchronous and control TX packets should be handled in the same manner
described for multi-packet buffering.
27.4.6.2 Isochronous and Synchronous Data Handling
Reception and transmission of isochronous and synchronous data should be handled in the following
manner:
• At the start of buffer processing, the beginning of the Next Buffer becomes the beginning of the
Current Buffer, as CNBCRn[BSA] is loaded into CCBCRn[BCA]. Additionally, the end of the
Next Buffer becomes the end of the Current Buffer, as CNBCRn[BEA] is loaded into
CCBCRn.[BFA]. (See Note 1 in Figure 27-20).
• A Buffer Start interrupt is generated (CSCRn[STS[3]] set), which informs software that hardware
has updated CCBCRn, cleared the local channel CSCRn[RDY] bit, and is available to accept the
next buffer. Software may then prepare the Next Buffer by writing CNBCRn[BSA],
CNBCRn[BEA], and CSCRn[RDY]. (See Note 2 in Figure 27-20).
• During the processing of the Current Buffer, CCBCRn[BCA] continues to mark which quadlet of
the isochronous or synchronous data is currently being processed. (See Note 3 in Figure 27-20).
• A Buffer Done interrupt is generated (CSCRn[STS[2]] set) when the last quadlet in the
Current Buffer has been successfully transmitted/received. (See Note 4 in Figure 27-20).
An example of buffer processing for isochronous and synchronous channels is provided in Figure 27-20.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
27-35