PXN20RM Datasheet, PDF (873/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
FLAG can be generated at B1 matches, when MODE[5] is cleared, or on either A1 or B1 matches when
MODE[5] is set. If subsequent matches occur on comparators A and B, the PWM pulses continue to be
generated, regardless of the state of the FLAG bit.
FORCMA and FORCMB bits allow the software to force the output flip-flop to the level corresponding
to a match on A1 or B1. The FLAG bit is not set by the FORCMA and FORCMB operations.
Some rules applicable to the OPWMB mode include:
• B1 matches have precedence over A1 matches if they occur at the same time within the same
counter cycle
• A1 = 0 match from cycle(n) has precedence over B1 match from cycle(n – 1)
• A1 matches are masked out if they occur after B1 match within the same cycle
• Any value written to A2 or B2 on cycle(n) is loaded to A1 and B1 registers at the following cycle
boundary (assuming (OU[n] in EMIOS_OUDR) is not asserted). The new values are used for A1
and B1 matches in cycle(n + 1)
Figure 28-48 shows the operation of the OPWMB mode regarding A1 and B1 matches and the transition
of the channel output pin. In this example, EDPOL is set to 0.
Cycle n
Write to A2
Cycle n + 1
Clock
Prescaler
Selected
6
6
Counter Bus
4
1
1
A1 Value 0x000004
A2 Value
0x000000
B1 Value 0x000006
A1 Match
A1 Match Posedge
Detection
A1 Match Negedge
Detection
B1 Match
B1 Match Negedge
Detection
0x000000
A1 Match Negedge
Detection
A1 Match Posedge Detection
B1 Match Negedge
Detection
Output Pin
FLAG Bit Set
EDPOL = 0
Figure 28-48. OPWMB Mode Matches and Flags
8
Time
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
28-51