PXN20RM Datasheet, PDF (453/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Memory Protection Unit (MPU)
Table 18-9. MPU_RGDn.Word3 Field Descriptions
Field
Description
PID Process Identifier. This 8-bit field specifies that the optional process identifier is to be included in the determination
of whether the current access hits in the region descriptor. This field is combined with the PIDMASK and included
in the region hit determination if MPU_RGDn.Word2[MxPE] is set.
Note: Master ID 0 is only able to drive the process identifier of 0.
PIDMASK Process Identifier Mask. This 8-bit field provides a masking capability so that multiple process identifiers can be
included as part of the region hit determination. If a bit in the PIDMASK is set, the corresponding bit of the PID is
ignored in the comparison. This field is combined with the PID and included in the region hit determination if
MPU_RGDn.Word2[MxPE] is set. For more information on the handling of the PID and PIDMASK, see
Section 18.4.1.1, Access Evaluation—Hit Determination.
VLD Valid. This bit signals the region descriptor is valid. Any write to MPU_RGDn.Word{0,1,2} clears this bit, but a write
to MPU_RGDn.Word3 sets or clears this bit depending on bit 31 of the write operand.
0 Region descriptor is invalid.
1 Region descriptor is valid.
18.3.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn)
As noted in Section 18.3.2.4.3, MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2), it is expected
that because system software may adjust the access controls within a region descriptor
(MPU_RGDn.Word2) only as different tasks execute, an alternate programming view of this 32-bit entity
is desired. If only the access controls are being updated, this operation should be performed by writing to
MPU_RGDAACn (alternate access control n) as stores to these locations do not affect the descriptor’s
valid bit.
The memory address therefore provides an alternate location for updating MPU_RGDn.Word2.
Offset: MPU_BASE + 0x800 + (4*n) (MPU_RGDAACn)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11 12 13
14
15
R0
W
0
M6RE M6WE M5RE
M5W
E
M4RE
M4W
E
0
0
0
0
0
0
M2PE
M2S
M
Reset –
–
–
–
–
–
–
–
–
–
– ––– –
–
16
R _M2S
WM
Reset –
17
18
19
20
21
22
M2UM
M1PE
r
w
x
M1SM
–
–
–
–
–
–
23
24
25
26
27 28
M1UM
M0PE M0SM
r
wx
–
–
–
– ––
29
30
31
M0UM
r
w
x
––
–
Figure 18-10. MPU RGD Alternate Access Control n (MPU_RGDAACn)
Because the MPU_RGDAACn register is another memory mapping for MPU_RGDn.Word2, the field
definitions shown in Table 18-10 are identical to those presented in Table 18-8.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
18-13