PXN20RM Datasheet, PDF (1148/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

IEEE 1149.1 Test Access Port Controller (JTAGC)
controller enters the update-IR state. It contains fields for controlling access to a resource, as well as
controlling single-step operation and exit from OnCE mode.
Although the OCMD is updated during the update-IR TAP controller state, the corresponding resource is
accessed in the DR scan sequence of the TAP controller, and as such, the update-DR state must be
transitioned through in order for an access to occur. In addition, the update-DR state must also be
transitioned through in order for the single-step and/or exit functionality to be performed, even though the
command appears to have no data resource requirement associated with it.
0
1
2
3
R
R/W GO EX
W
4
5
6
7
8
9
RS
Reset: 0
0
0
0
0
0
0
0
1
0
Figure 35-8. OnCE Command Register (OCMD)
Table 35-3. e200z0 and e200z6 OnCE Register Addressing
RS
000 0000 – 000 0001
000 0010
000 0011 – 000 1111
001 0000
001 0001
001 0010
001 0011 – 001 1111
010 0000
010 0001
010 0010
010 0011
010 0100
010 0101
010 0110 – 010 1011
010 1100
010 1101
010 1110 – 010 1111
011 0000
011 0001
011 0010
011 0011
Register Selected
Reserved
JTAG ID (read-only)
Reserved
CPU Scan Register (CPUSCR)
No Register Selected (Bypass)
OnCE Control Register (OCR)
Reserved
Instruction Address Compare 1 (IAC1)
Instruction Address Compare 2 (IAC2)
Instruction Address Compare 3 (IAC3)
Instruction Address Compare 4 (IAC4)
Data Address Compare 1 (DAC1)
Data Address Compare 2 (DAC2)
Reserved
Debug Counter Register (DBCNT)¹
Debug PCFIFO (PCFIFO) (read-only)¹
Reserved
Debug Status Register (DBSR)
Debug Control Register 0 (DBCR0)
Debug Control Register 1 (DBCR1)
Debug Control Register 2 (DBCR2)
35-14
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor