PXN20RM Datasheet, PDF (1205/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
MCKO
MSEO[
MDO[1:0] 00 11 00 00 00 11 10 11 00 11 10 10 11 11 01 11 10 10 10 11 01 11 00
TCODE = 12
Source Processor = 0b0000
Number of Sequential Instructions = 3
Full Target Address = 0xDEAD_FACE
Note: This is representative only. The PXN20 supports only Full-Port Mode with 12 MDO pins.
Figure 36-40. Program Trace—Indirect Branch with Sync. Message
36.6.10.4 Data Trace
This section deals with the data trace mechanism supported by the Nexus3+ module. Data trace is
implemented via data write messaging (DWM) and data read messaging (DRM), as per the IEEE-ISTO
5001-2003 standard.
36.6.10.4.1 Data Trace Messaging (DTM)
Data trace messaging for e200z6 is accomplished by snooping the e200z6 virtual data bus (between the
CPU and MMU), and storing the information for qualifying accesses (based on enabled features and
matching target addresses). The Nexus3+ module traces all data access that meet the selected range and
attributes.
NOTE
Data trace is only performed on the e200z6 virtual data bus. This allows for
data visibility for the incorporated data cache. Only e200z6 CPU initiated
accesses are traced.
Data trace messaging can be enabled in one of two ways:
• Setting the TM field of the DC1 register to enable data trace (DC1[TM]).
• Using WT[DTS] to enable data trace on watchpoint hits (e200z6 watch points are configured
within the Nexus1 module)
36.6.10.4.2 DTM Message Formats
The Nexus3 module supports five types of DTM messages: data write, data read, data write
synchronization, data read synchronization and error messages.
Data Write Messages
The data write message contains the data write value and the address of the write access, relative to the
previous data trace message. Data write message information is messaged out in the following format:
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-55