PXN20RM Datasheet, PDF (180/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
7.5 Resets
This section describes the reset operation of the PLL, including power-on reset and normal resets. The
reset values of registers and signals are provided in other sections.
7.5.1 Clock Mode Selection
The initial clock mode is reflected in the MODE, PLLSEL, and PLLREF bits of the synthesizer status
register (SYNSR) as well as the ESYNCR1[CLKCFG] bit field. The clock mode can be modified by
writing to the CLKCFG bit field. The synthesizer status register then reflects the newly-selected PLL clock
mode.
Table 7-13 summarizes clock mode selection.
Table 7-13. Clock Mode Selection
Clock Mode
PLL Off mode
Normal mode with external reference
Normal mode with crystal reference
Reserved
Synthesizer Status Register (SYNSR)
MODE, PLLSEL, and PLLREF Bits
MODE/
CLKCFG2
0
1
1
1
PLLSEL/
CLKCFG1
X
1
1
0
PLLREF/
CLKCFG0
X
0
1
0
7.5.1.1 Power-On Reset (POR)
The PLL will not operate until the POR signal has been deasserted and the ESYNCR1[CLKCFG] bitfield
set for PLL mode. Refer to PXN20 Microcontroller Data Sheet for these thresholds. At this point, the PLL
operates in self-clocked mode (SCM) until a valid reference clock is detected by the internal clock monitor
circuit.
Internal to the PLL, the VCO is held in reset until the negation of the POR signal. This prevents the PLL
from attempting to lock before its supplies are within specification, which can cause VCO/loop gain to be
lower than what the analog loop is designed for.
7.5.1.2 External Reset
After POR has negated, the PLL defaults to PLL Off mode and the default clock source for the system
clock is the 16 MHz_IRC. After reset exit, the PLL may be configured for operation and after lock may
be selected as the system clock source.
After the initial lock with the default MFD (assuming normal mode was selected), ESYNCR1 may be
written to modify the MFD for the desired operating frequency. The PLL may not lock with an MFD and
crystal frequency combination that attempts to force the VCO outside of its operating range.
7-18
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor