PXN20RM Datasheet, PDF (907/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
Table 29-11. CANx_ESR Field Descriptions (continued)
Field
Description
IDLE
CAN Bus IDLE State. This status bit indicates when CAN bus is in IDLE state.
0 No such occurrence.
1 CAN bus is now IDLE.
TXRX
Current FlexCAN Status (Transmitting/Receiving). This status bit indicates if FlexCAN is transmitting or
receiving a message when the CAN bus is not in IDLE state. This bit has no meaning when IDLE is asserted.
0 FlexCAN is receiving a message (IDLE = 0).
1 FlexCAN is transmitting a message (IDLE = 0).
FLT_CONF
Fault Confinement State. This status bit indicates the confinement state of the FlexCAN module. If the LOM bit
in the CANx_CTRL is asserted, the FLT_CONF field indicates “Error Passive”. Since the CANx_CTRL is not
affected by soft reset, the FLT_
CONF field is not affected by soft reset if the LOM bit is asserted.
00 Error active.
01 Error passive.
1n Bus off.
BOFF_INT
Bus Off Interrupt. This status bit is set when FlexCAN is in the bus off state. If CANx_CTRL[BOFF_MSK] is set,
an interrupt is generated to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
0 No such occurrence.
1 FlexCAN module is in “Bus Off” state.
ERR_INT
Error Interrupt. This status bit indicates that at least one of the error bits (bits 16–21) is set. If
CANx_CTRL[ERR_MSK] is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1.
Writing 0 has no effect.
0 No such occurrence.
1 Indicates setting of any error bit in the CANx_ESR.
29.3.4.7 Interrupt Masks 2 Register (CANx_IMASK2)
This register allows any number of a range of 32 message buffer interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (that is, when the corresponding CANx_IFLAG2 bit
is set).
Offset: Base + 0x0024
Access: User read/write
0
R _BUF
W ^63M
Reset 0
1
BUF
62M
0
2
BUF
61M
0
3
BUF
60M
0
4
BUF
59M
0
5
BUF
58M
0
6
BUF
57M
0
7
BUF
56M
0
8
BUF
55M
0
9
BUF
54M
0
10
BUF
53M
0
11
BUF
52M
0
12
BUF
51M
0
13
BUF
50M
0
14
BUF
49M
0
15
BUF
48M
0
16
R _BUF
W ^47M
Reset 0
17
BUF
46M
0
18
BUF
45M
0
19
BUF
44M
0
20
BUF
43M
0
21
BUF
42M
0
22
BUF
41M
0
23
BUF
40M
0
24
BUF
39M
0
25
BUF
38M
0
26
BUF
37M
0
27
BUF
36M
0
28
BUF
35M
0
29
BUF
34M
0
30
BUF
33M
0
31
BUF
32M
0
Figure 29-11. Interrupt Masks 2 Register (CANx_IMASK2)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
29-23