PXN20RM Datasheet, PDF (210/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Table 8-18. Pin Data Output Register to Pin Mapping (continued)
SIU_GPDOn
112_115
116_119
120_123
124_127
128_131
132_135
136_139
140_143
144_147
148_151
152_154
Address Offset
0x0670
0x0674
0x0678
0x067C
0x0680
0x0684
0x0688
0x068C
0x0690
0x0694
0x0698
Pins
PH0–PH3
PH4–PH7
PH8–PH11
PH12–PH15
PJ0–PJ3
PJ4–PJ7
PJ8–PJ11
PJ12–PJ15
PK0–PK3
PK4–PK7
PK8–PK10
8.3.2.15 GPIO Pin Data Input Registers (SIU_GPDI0_3–SIU_GPDI152_154)
The definition of the SIU_GPDI0_3 register is given in Figure 8-18. All other SIU_GPDIn registers follow
the same pattern where 4 GPDI bits are placed in a 32-bit word, with one bit per byte. Each of the 155
GPDI bits correspond to the port pin (Table 8-20). Gaps exist in this memory space where the pin is not
available in the package.
The SIU_GPDIn registers are read-only registers that allow software to read the input state of an external
GPIO pin. Each byte of a register represents the input state of a single external GPIO pin. If the GPIO pin
is configured as an output, and the input buffer enable (IBE) bit is set in the associated Pad Configuration
Register, the SIU_GPDIn register reflects the actual state of the output pin.
Offset: SIU_BASE + 0x0800–SIU_BASE+0x0891
0
1
2
3
4
5
R0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
6
7
8
0 PDI0 0
0
U
0
Access: User read-only
9
10
11
12
13
14
15
0 0 0 0 0 0 PDI1
000000U
16
R0
W
Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0 PDI2 0 0 0 0 0 0 0 PDI3
0
0
0
0
0
0
U
0
0
0
0
0
0
0
U
Figure 8-18. GPIO Pin Data Input Register 0–3 (SIU_GPDI0_3)
Table 8-19. SIU_GPDIn Field Description
Field
PDIn
Description
Pin Data In. This bit reflects the input state on the external GPIO pin associated with the register.
0 Signal on pin is less than or equal to V_IL.
1 Signal on pin is greater than or equal to V_IH.
8-28
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor