PXN20RM Datasheet, PDF (269/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Chapter 10
Interrupts and Interrupt Controller (INTC)
10.1 Introduction
This chapter describes the interrupts and the interrupt controller (INTC), which schedules interrupt
requests (IRQs) from software and internal peripherals to the e200z6 and e200z0 cores. The INTC
provides interrupt prioritization and preemption, interrupt masking, interrupt priority elevation, and
protocol support. The INTC supports 316 interrupt requests.
The INTC has two independent sets of priority arbitration/comparison, request selection, vector encoder
and acknowledge logic—one set for each CPU. This allows each CPU to handle its software-assigned
interrupt requests independently of the other CPU’s operation, and provides flexibility for the user to
decide which core should handle which interrupt sources in the application. This flexibility comes from a
set of configuration bits that allows any interrupt source to generate an interrupt request to either the Z6 or
Z0 or to both the Z6 and Z0 cores.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority can be raised temporarily so that all tasks which share the resource cannot preempt each other.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests,
i.e., by using application software to assert an interrupt request. These same software settable interrupt
requests also can be used to break the work involved in servicing an interrupt request into a high priority
portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request,
but then the ISR can assert a software settable interrupt request to finish the servicing in a lower priority
ISR.
10.1.1 Block Diagram
Interrupts implemented by the MCU are defined in the e200z6 PowerPC™ Core Reference Manual.
Figure 10-1 shows a block diagram of the interrupt controller (INTC).
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
10-1