PXN20RM Datasheet, PDF (417/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Semaphores
Multiple gate values can be read in a single access, but only a single gate at a time can be updated via a
write operation. 16- and 32-bit writes to multiple gates are allowed, but the write data operand must update
the state of a single gate only. A byte write data value of 0x03 is defined as no operation and does not affect
the state of the corresponding gate register. Attempts to write multiple gates in a single-aligned access with
a size larger than an 8-bit (byte) reference generate an error termination and do not allow any gate state
changes.
Offset: SEMA4_BASE + n (n = 0, 1, 2,..., 15)
Access: User read/write
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
W
GTFSM
Reset
0
0
0
0
0
0
0
0
Figure 15-2. SEMA4 Gate n Register (SEMA4_GATEn)
Table 15-2. SEMA4_GATEn Field Descriptions
Field
Description
GTFSM
Gate Finite State Machine. The hardware gate is maintained in a three-state implementation, defined as:
00 The gate is unlocked (free).
01 The gate has been locked by processor 0.
10 The gate has been locked by processor 1.
11 This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as no operation
and do not affect the gate state machine.
Note: The state of the gate reflects the last processor that locked it, which can be useful during system debug.
15.3.2.2 Semaphores Processor n IRQ Notification Enable (SEMA4_CP{0,1}INE)
The application of a hardware semaphore module provides an opportunity for implementation of helpful
system-level features. An example is an optional mechanism to generate a processor interrupt after a failed
lock attempt. Traditional software gate functions execute a spin-wait loop in an effort to obtain and lock
the referenced gate. With this module, the processor that fails in the lock attempt could continue with other
tasks and allow a properly-enabled notification interrupt to return its execution to the original lock
function.
The optional notification interrupt function consists of two registers for each processor: an interrupt
notification enable register (SEMA4_CPnINE) and the interrupt request register (SEMA4_CPnNTF). To
support implementations with more than 16 gates, these registers can be referenced with aligned 16- or
32-bit accesses. For the SEMA4_CPnINE registers, unimplemented bits read as zeroes and writes are
ignored.
Offset: SEMA4_BASE + 0x0040 (SEMA4_CP0INE)
SEMA4_BASE + 0x0048 (SEMA4_CP1INE)
Access: User read/write
0
R
INE0
W
1
INE1
2
INE2
3
INE3
4
INE4
5
INE5
6
INE6
7
INE7
8
INE8
9
10
11
12
13
14
15
INE9 INE10 INE11 INE12 INE13 INE14 INE15
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-3. Semaphores Processor n IRQ Notification Enable (SEMA4_CP{0,1}INE)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
15-5