PXN20RM Datasheet, PDF (1091/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
Table 34-3. MSR Field Descriptions (continued)
Field
Description
JSTART
This status bit indicates that an injected conversion is ongoing.
0 Injected conversion is not occurring now.
1 Injected conversion is occurring.
CTUSTART
This status bit indicates that a CTU conversion is ongoing. This bit is set when a CTU trigger pulse is received
and the CTU conversion starts. When CTU trigger mode is enabled, this bit is automatically reset when the
conversion is completed. Otherwise, if Control Mode is enabled this bit is reset when the CTU is disabled
(CTUEN = 0).
0 CTU conversion is not occurring now.
1 CTU conversion is occurring.
Note: The CTU is not implemented on the PXN20.
CHADDR Channel under measure address. This bitfield indicates which channel (0 to 95) is under measure.
ACKO
Auto clock off enable. This status bit indicates whether the Auto clock off feature is activated.
0 Auto clock off feature is deactivated.
1 Auto clock off feature is activated.
OFFREFRESH This status bit indicates that an offset refresh is ongoing.
0 No offset refresh.
1 Offset refresh during idle mode when ADC is waiting for a new start of conversion.
OFFCANC
This status bit indicates that an offset cancellation is ongoing.
0 Offset cancellation is not occurring.
1 Offset cancellation is occurring.
ADCSTATUS This bitfield displays the ADC status, as follows:
ADCSTATUS
Description
0b000
0b001
0b010
0b100
0b110
IDLE or Offset cancel/refresh
Power Down
Wait State
Sample
Conversion
34.3.2.3 Interrupt Status Register (ISR)
The ISR register contains interrupt status bits for the ADC.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
34-11