PXN20RM Datasheet, PDF (1020/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
the eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set and the internal commit bit iCMT is
cleared.
31.4.5.2.4 DMA Controlled SCI Data Frame Transmission
In this mode, the eSCI module handles the generation of data frames internally.
When new data required for transmission, the module generates the transmit DMA request and the DMA
controller delivers the required data via write accesses to the eSCI SCI Data Register (eSCI_SDR). The
write access to the low byte of the eSCI SCI Data Register (eSCI_SDR) triggers the transmission of the
data. The write access to the high byte of the eSCI SCI Data Register (eSCI_SDR) triggers no internal
operation.
The application requests the eSCI module to enter this mode by setting the TXDMA bit in the eSCI Control
Register 2 (eSCI_CR2). From this point in time, the module starts the generation of DMA requests and
frame transmission. Before entering this mode, the application should perform the following actions:
1. Configure the module for SCI mode.
2. Enable the transmitter by setting TE in the eSCI Control Register 1 (eSCI_CR1) to 1.
3. Set up the DMA controller channel and provide frame data in system memory.
Figure 31-26 shows an overview of the DMA-controlled date frame transmission.
System Memory
DATA 1
DATA 2
DMA
Controller
TX DMA
channel
eSCI
DATA N
DATA 1
DATA N
SCI Data frame
Figure 31-26. DMA Controlled SCI Data Frame Generation
NOTE
A received SCI frame is not written into the SCI Data Registers and the
Overrun (OR) flag is not set in the SCI Status Register 1 (SCISR1), if:
• The eSCI has received the last data bit of an SCI frame n,
• The Receive Data Register Full (RDRF) flag is still set in the SCISR1
after the reception of SCI frame n-1, and
31-30
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor