PXN20RM Datasheet, PDF (740/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
RC1
single RX
RC2
single TX
RC1
RC3
double TX (commit side)
RC3
double TX (transmit side)
RC1
Figure 26-137. Message Buffer Reconfiguration Scheme
26.6.9 Receive FIFOs
This section provides the functional description of the two receive FIFOs.
26.6.9.1 Overview
The two receive FIFOs implement the queued message buffer concept defined by the FlexRay
Communications System Protocol Specification, Version 2.1 Rev A. One FIFO is assigned to channel A,
the other FIFO is assigned to channel B. Both FIFOs work completely independent from each other.
The message buffer structure of each FIFO is described in Section 26.6.3.3, Receive FIFO. The area in the
FlexRay memory for each of the two FIFOs is characterized by:
• The FIFO system memory base address
• The index of the first FIFO entry given by Receive FIFO Start Index Register (RFSIR)
• The number of FIFO entries and the length of each FIFO entry as given by Receive FIFO Depth
and Size Register (RFDSR)
26.6.9.2 FIFO Configuration
The FIFOs can be configured for two different locations of the system memory base address via the FIFO
address mode bit FAM in the Module Configuration Register (MCR).
26.6.9.2.1 Single System Memory Base Address Mode
This mode is configured, when the FIFO address mode flag MCR[FAM] is set to 0. In this mode, the
location of the system memory base address for the FIFO buffers is System Memory Base Address
Register (SYMBADR).
26.6.9.2.2 Dual System Memory Base Address Mode
This mode is configured, when the FIFO address mode flag MCR[FAM] is set to 1. In this mode, the
location of the system memory base address for the FIFO buffers is Receive FIFO System Memory Base
Address Register (RFSYMBADR).
26-126
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor