PXN20RM Datasheet, PDF (498/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Periodic Interrupt Timer (PIT)
Table 22-2. PIT Memory Map (continued)
Offset from
PIT_BASE
(0xFFFE_0000)
Register
Access Reset Value Section/Page
Timer Channel 7
0x0160
0x0164
0x0168
0x016C
LDVAL7—Timer 7 Load Value Register
CVAL7—Timer 7 Current Value Register
TCTRL7—Timer 7 Control Register
TFLG7—Timer 7 Flag Register
Timer Channel 8
0x0170
LDVAL8—Timer 8 Load Value Register
0x0174
CVAL8—Timer 8 Current Value Register
0x0178
TCTRL8—Timer 8 Control Register
0x017C
TFLG8—Timer 8 Flag Register
0x0180–0x03FF Reserved
1 _{Some bits are read-only.}
R/W 0x0000_0000
R/W
R/W¹
R/W¹
0x0000_0000
0x0000_0000
0x0000_0000
22.3.2.2/22-5
22.3.2.3/22-5
22.3.2.4/22-6
22.3.2.5/22-7
R/W 0x0000_0000
R/W
R/W¹
R/W¹
0x0000_0000
0x0000_0000
0x0000_0000
22.3.2.2/22-5
22.3.2.3/22-5
22.3.2.4/22-6
22.3.2.5/22-7
22.3.2 Register Descriptions
This section lists the PIT registers and describes the registers and their bit fields.
22.3.2.1 PIT Module Control Register (PITMCR)
This register controls whether the timer clocks should be enabled and whether the timers should run in
debug mode.
Offset: PIT_BASE + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MDIS FRZ
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Figure 22-2. PIT Module Control Register (PITMCR)
22-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor