PXN20RM Datasheet, PDF (913/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
Once the highest priority MB is selected, it is transferred to a temporary storage space called serial
message buffer (SMB), which has the same structure as a normal MB but is not user accessible. This
operation is called “move-out” and after it is done, write access to the corresponding MB is blocked (if the
AEN bit in CANx_MCR is asserted). The write access is released in the following events:
• After the MB is transmitted
• FlexCAN enters in HALT or BUS OFF
• FlexCAN loses the bus arbitration or there is an error during the transmission
At the first opportunity window on the CAN bus, the message on the SMB is transmitted according to the
CAN protocol rules. FlexCAN transmits as many as 8 data bytes, even if the data length code (DLC) value
is bigger.
29.4.3 Receive Process
The CPU prepares a message buffer for frame reception by executing the following steps:
1. If the MB has a pending transmission, write an ABORT code (‘1001’) to the code field of the
control and status word to request an abortion of the transmission, then read back the code field
and the CANx_IFLAG1/2 register to check if the transmission was aborted (see Section 29.4.5.1,
Transmission Abort Mechanism). If backwards compatibility is desired (AEN in CANx_MCR
negated), just write ‘1000’ to the code field to inactivate the MB, but then the pending frame may
be transmitted without notification (see Section 29.4.5.2, Message Buffer Deactivation). If the MB
already programmed as a receiver, just write ‘0000’ to the code field of the control and status word
to keep the MB inactive.
2. Write the ID word.
3. Write ‘0100’ to the code field of the control and status word to activate the MB.
After the MB is activated in the third step, it can receive frames that match the programmed ID. At the end
of a successful reception, the MB is updated by the MBM as follows:
1. The value of the free-running timer is written into the time stamp field.
2. The received ID, data (8 bytes at most), and length fields are stored.
3. The code field in the control and status word is updated (see Table 29-4 and Table 29-5 in
Section 29.3.2, Message Buffer Structure).
4. A status flag is set in the interrupt flag register and an interrupt is generated if allowed by the
corresponding interrupt mask register bit.
Upon receiving the MB interrupt, the CPU should service the received frame using the following
procedure:
1. Read the control and status word (mandatory – activates an internal lock for this buffer).
2. Read the ID field (optional – needed only if a mask was used).
3. Read the data field.
4. Read the free-running timer (optional – releases the internal lock).
Upon reading the control and status word, if the BUSY bit is set in the code field, then the CPU should
defer the access to the MB until this bit is negated. Reading the free-running timer is not mandatory. If not
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
29-29