PXN20RM Datasheet, PDF (1251/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Note that T0, A0, D0 are the least significant bits where:
• Tx = TCODE number (fixed)
• Sx = Source processor (fixed)
• Zx = Data size (fixed)
• Ax = Unique portion of the address (variable)
• Dx = Write data (variable 8-bit, 16-bit, or 32-bit)
Table 36-64. Direct Write Message Example (12 MDO / 2 MSEO)
Clock
0
MDO[11:0]
11 10 9
8
7
6
5
4
3
2
1
0
XXXXXXXXXXXX
1
Z1 Z0 S3 S2 S1 S0 T5 T4 T3 T2 T1 T0
2
0 0 0 0 0 0 0 A3 A2 A1 A0 Z2
3
X X X X D7 D6 D5 D4 D3 D2 D1 D0
MSEO[1:0]
1
1
0
0
0
1
1
1
State
Idle (or end of last
message)
Start Message
End Packet
End Packet/End
Message
36.7.9.7 IEEE 1149.1 (JTAG) RD/WR Sequences
This section contains example JTAG/OnCE sequences used to access resources.
36.7.9.7.1
JTAG Sequence for Accessing Internal Nexus Registers
Table 36-65. Accessing Internal Nexus2+ Registers via JTAG/OnCE
Step #
1
2
3
4
5
6
7
8
9
10
11
12
13
TMS Pin
1
0
0
0
1
1
1
0
0
0
1
1
0
Description
IDLE  SELECT-DR_SCAN
SELECT-DR_SCAN  CAPTURE-DR (Nexus command register value loaded in shifter)
CAPTURE-DR  SHIFT-DR
(7) TCK clocks issued to shift in direction (rd/wr) bit and first 6 bits of Nexus reg. addr.
SHIFT-DR  EXIT1-DR (7th bit of Nexus reg. shifted in)
EXIT1-DR  UPDATE-DR (Nexus shifter is transferred to Nexus command register)
UPDATE-DR  SELECT-DR_SCAN
SELECT-DR_SCAN  CAPTURE-DR (Register value is transferred to Nexus shifter)
CAPTURE-DR  SHIFT-DR
(31) TCK clocks issued to transfer register value to TDO pin while shifting in TDI value
SHIFT-DR  EXIT1-DR (MSB of value is shifted in/out of shifter)
EXIT1-DR  UPDATE -DR (if access is write, shifter is transferred to register)
UPDATE-DR  RUN-TEST/IDLE (transfer complete - Nexus controller to reg. select state)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-101