PXN20RM Datasheet, PDF (848/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
In order to guarantee coherent access, reading EMIOS_CADR[n] forces B1 to be updated with the content
of register A1. At the same time transfers between B2 and B1 are disabled until the next read of
EMIOS_CBDR[n] register. Reading EMIOS_CBDR[n] register forces B1 be updated with A1 register
content and re-enables transfers from B2 to B1, to take effect at the next trailing edge capture. Transfers
from B2 to A1 are not blocked at any time.
The input pulse width is calculated by subtracting the value in B1 from A2.
Figure 28-20 shows how the unified channel can be used for input pulse-width measurement.
EDPOL = 1
B
A
B
A
B
Input Signal¹
Selected
Counter Bus
0x000500
0x001000
0x001100
0x001250
0x001525
FLAG
Set Event
A2 (Captured)
Value²
B1 Value³
B2 (Captured)
Value
A1 Value³
0xxxxxxx
0xxxxxxx
0xxxxxxx
0xxxxxxx
0xxxxxxx
0xxxxxxx
0x001000
0xxxxxxx
0x001100
0x001000
0x001000
0x001000
0x001100
0x001000
0x001250
0x001000
0x001525
0x001250
0x001250
0x001250
Notes: ¹ After input filter
2 _{EMIOS_CADR[n] = A2}
3 _{EMIOS_CBDR[n] = B1}
Figure 28-20. Input Pulse-Width Measurement Example
0x0016A0
0x001525
0x001250
0x0016A0
0x001250
Figure 28-21 shows the A1 and B1 updates when EMIOS_CADR[n] and EMIOS_CBDR[n] register reads
occur. The A1 register has always coherent data related to A2 register. When EMIOS_CADR[n] read is
performed, the B1 register is loaded with the A1 register content. This guarantees that the data in register
B1 always has the coherent data related to the last EMIOS_CADR[n] read. The B1 register updates remain
locked until EMIOS_CBDR[n] read occurs. If EMIOS_CADR[n] read is performed, B1 is updated with
A1 register content even if the B1 update is locked by a previous EMIOS_CADR[n] read operation.
28-26
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor