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PXN20RM Datasheet, PDF (1068/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller | |||
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Inter-Integrated Circuit Bus Controller Module (I2C)
system back into a ready-for-I2C-transfer state. The advantage over the two other solutions is that
this does not require CPU intervention or a second DMA channel. This comes at the cost of 64
bytes RAM (two TCDs), some system bus transfer overhead, and a little increase in application
code complexity. On the system level, no higher priority DMA requests must occur during the
scatter-gather process because those can result in a slow reaction.
Example latencies for a 32 MHz system with a full speed 32-bit AHB bus and an I2C connected via half
speed IPI bus:
⢠Accessing the I2C from the DMA controller via IPI bus typically requires four cycles (consecutive
accesses to the I2C could be faster):
4 x TIPI = 4 / 16 MHz = 250 ns
Eqn. 32-6
⢠Reloading a new TCD (8 ï´ 32 bit) via AHB to the DMA controller (scatter/gather process):
8 x TAHB = 8 / 32 MHz = 250 ns
Eqn. 32-7
With the DMA scatter-gather process, the required IBCR access can be done in 0.5 ïs, leaving a large
margin of 19.5 ïs for additional system delays. The slow reaction case can be prevented in this way. The
system user must decide which usage model suits his overall requirements best.
32-24
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
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