PXN20RM Datasheet, PDF (274/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
the size of a write does not affect the operation of the write. Those values and sizes written to this register
neither update the INTC_EOIR_PRCn contents nor affect whether the LIFO pops. For possible future
compatibility, write four bytes of all 0s to the INTC_EOIR_PRCn. The timing relationship between
popping the LIFO and disabling recognition of external input has no restriction. The writes can happen in
either order.
However, disabling recognition of the external input before popping the LIFO eases the calculation of the
maximum stack depth at the cost of postponing the servicing of the next interrupt request.
10.1.3.2 Hardware Vector Mode
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral
to when the processor is performing useful work to service the interrupt request needs to be minimized.
The INTC can be optimized to support this goal through the hardware vector mode, where a unique vector
is provided for each interrupt request source. It also provides 16 priorities so that lower priority ISRs do
not delay the execution of higher priority ISRs. Since each individual application has different priorities
for each source of interrupt request, the priority of each interrupt request is configurable.
Typical program flow for hardware vector mode is shown in Figure 10-6.
NOTE:
‘b ISR_n’ is technically
part of the handler.
Address
IVPR + offset[0]
IVPR + offset[1]
IRQ[n]
taken
IVPR + offset[2]
IVPR + n [0x0010]
IVPR + offset[N – 1]
Instructions
b handler 0
•••
b handler 1
•••
b handler 2
•••
b handler n
•••
b handler N – 1
handler 0
handler n
handler N
Address IVPR + offset[N – 1] contains the 316th interrupt vector and is the last
usable interrupt vector address in the interrupt memory map for this device.
Prolog
ISR
Epilog
•••
Prolog
ISR
Epilog
•••
Prolog
ISR
Epilog
N is the maximum number of usable interrupt vectors, which equals 316, and includes 26 reserved IRQ vectors
and eight software-settable IRQ vectors.
Figure 10-6. Program Flow–Hardware Vector Mode
In hardware vector mode, the interrupt exception handler address is specific to the peripheral or software
settable interrupt source rather than being common to all of them. No IVOR is used. The interrupt
exception handler address is calculated by hardware as shown in Figure 10-7 for the Z0 core and in
Figure 10-8 for the Z6 core. The upper half of the interrupt vector prefix register (IVPR) is added to an
offset which corresponds to the peripheral or software interrupt source which caused the interrupt request.
The offset matches the value in the Interrupt Vector field, INTC_IACKR_PRCn[INTVEC]. Each interrupt
exception handler address is aligned on a quad word (16-byte) boundary for the Z6 and on a word
boundary (4-byte) for the Z0. IVOR4 is not used in this mode, and software does not need to read
INTC_IACKR_PRCn to get the interrupt vector number.
10-6
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor