PXN20RM Datasheet, PDF (959/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
successful communication with a SPI master. The SPI slave mode transfer attributes are set in the
DSPI_CTAR0.
30.4.3.3 FIFO Disable Operation
The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO. The DSPI
operates as a double-buffered simplified SPI when the FIFOs are disabled. The TX and RX FIFOs are
disabled separately. The TX FIFO is disabled by writing a ‘1’ to the DIS_TXF bit in the DSPI_MCR. The
RX FIFO is disabled by writing a ‘1’ to the DIS_RXF bit in the DSPI_MCR.
The FIFO disable mechanisms are transparent to the user and to host software; Transmit data and
commands are written to the DSPI_PUSHR and received data is read from the DSPI_POPR. When the TX
FIFO is disabled the TFFF, TFUF and TXCTR fields in DSPI_SR behave as if there is a one-entry FIFO
but the contents of the DSPI_TXFR registers and TXNXTPTR are undefined. When the RX FIFO is
disabled the RFDF, RFOF and RXCTR fields in the DSPI_SR behave as if there is a one-entry FIFO but
the contents of the DSPI_RXFR registers and POPNXTPTR are undefined.
The TX and RX FIFOs must be disabled only if the application’s operating mode requires the FIFO to be
disabled. A FIFO must be disabled before it is accessed. Failure to disable a FIFO prior to a first FIFO
access is not supported, and may result in incorrect results.
30.4.3.4 Transmit First-In First-Out (TX FIFO) Buffering Mechanism
The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX FIFO holds
four entries, each consisting of a command field and a data field. SPI commands and data are added to the
TX FIFO by writing to the DSPI PUSH TX FIFO Register (DSPI_PUSHR). For more information on
DSPI_PUSHR, refer to Section 30.3.2.6, DSPI PUSH TX FIFO Register (DSPI_PUSHR). TX FIFO
entries can only be removed from the TX FIFO by being shifted out or by flushing the TX FIFO.
The TX FIFO counter field (TXCTR) in the DSPI Status Register (DSPI_SR) indicates the number of valid
entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data is
transferred into the shift register from the TX FIFO. For more information on DSPI_SR, refer to
Section 30.3.2.4, DSPI Status Register (DSPI_SR).
The TXNXTPTR field indicates which TX FIFO entry is transmitted during the next transfer. The
TXNXTPTR contains the positive offset from DSPI_TXFR0 in number of 32-bit registers. For example,
TXNXTPTR = 0b0010 (2) means that the DSPI_TXFR2 contains the SPI data and command for the next
transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the
shift register.
30.4.3.4.1 Filling the TX FIFO
Host software or the eDMA controller can add (push) entries to the TX FIFO by writing to the
DSPI_PUSHR. When the TX FIFO is not full, the TX FIFO fill flag (TFFF) in the DSPI_SR is set. The
TFFF bit is cleared when TX FIFO is full and the eDMA controller indicates that a write to DSPI_PUSHR
is complete or by host software writing a ‘1’ to the TFFF in the DSPI_SR. The TFFF can generate a DMA
request or an interrupt request. See Section 30.4.12.2, Transmit FIFO Fill Interrupt or DMA Request
(TFFF), for details.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
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