PXN20RM Datasheet, PDF (804/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
27.4.6 DMA Controller (Ping-Pong Buffering)
Using the MLB DMA Controller with ping-pong buffering dictates a particular method used for
transferring data between hardware channels and system memory. When the MLB hardware channels are
configured in this mode, the CCBCRn and CNBCRn registers are used to configure and monitor the
system memory Current Buffer and Next Buffer, respectively.
Channels use ping-pong buffering when CECRn[MDS[1:0]] = 00. The Current Buffer and Next Buffer are
independent system memory buffers, which allow hardware to support the ping-pong buffering. Each is
addressed using two 16-bit address pointers, as follows:
• Buffer Start Address (CNBCRn[BSA]) – defines the beginning address of the Next Buffer in
system memory
• Buffer End Address (CNBCRn[BEA]) – determines the end of the Next Buffer in system memory
• Buffer Current Address (CCBCRn[BCA]) – defines the beginning of the Current Buffer in system
memory
• Buffer Final Address (CCBCRn[BFA]) – defines the end of the Current Buffer in system memory
27.4.6.1 Asynchronous and Control Packet Handling
The Current Buffer and Next Buffer can be configured for either multi-packet or single-packet buffering,
when receiving and transmitting asynchronous and control packet data. Multi-packet buffering allows the
system to reduce the interrupt load at the expense of larger system memory buffers. Single-packet
buffering allows system memory buffer size to be reduced at the expense of increasing the interrupt rate.
An example of multi-packet buffering for asynchronous and control channels is provided in Figure 27-19.
27-32
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor