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PXN20RM Datasheet, PDF (1165/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller
Nexus Development Interface (NDI)
results in synchronous loading of the BYPASS instruction. Asynchronous entry into the test-logic-reset
state results in asynchronous loading of the BYPASS instruction. During the Capture-IR TAP controller
state, the instruction register is loaded with the value of the previously executed instruction, making this
value the register’s read value when the TAP controller is sequenced into the Shift-IR state.
3
2
1
0
R
Previous Instruction Opcode
W
Instruction Opcode
Reset:
BYPASS Instruction Opcode (0xF)
Figure 36-5. 4-Bit Instruction Register
36.5.4.3 Nexus Device ID Register (DID)
The NPC device identification register, shown in Figure 36-6, allows the part revision number, design
center, part identification number, and manufacturer identity code of the device to be determined through
the auxiliary output port, and serially through TDO. See Section 36.5.5.2.3, NPC IEEE 1149.1-2001
(JTAG) TAP. This register is read-only.
Reg Index: 0x00
Access: User read only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
PRN
DC
PIN
W
Reset 1 *
*
*
*
1
00
0
00
1
00
1
10
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PIN (continued)
MIC
1
W
Reset 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1
Figure 36-6. Nexus Device ID Register (DID)
1 Part Revision Number default value is 0x0 for the device’s initial mask set and changes for each mask set revision.
Table 36-8. DID Field Descriptions
Field
PRN
DC
PIN
MIC
bit 0
Description
Part Revision Number. Contains the revision number of the part. This field changes with each revision of the device
or module.
Design Center. Indicates the Freescale design center. This value is 0x20.
Part Identification Number. Contains the part number of the device.
Manufacturer Identity Code. Contains the reduced Joint Electron Device Engineering Council (JEDEC) ID for
Freescale, 0x00E.
Fixed Per JTAG 1149.1. Always set to 1.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-15