PXN20RM Datasheet, PDF (240/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
8.3.2.47 Masked Serial GPO Register for DSPI_A Low (SIU_DSPIAL)
The SIU_DSPIAL register allows any combination of bits in the bottom half of the 32-bit serialized data
frame from DSPI_A to be updated with a single 32-bit write operation, while allowing other bits to
maintain their previous state. This is accomplished by writing a 16-bit masked value coherently with an
update value contained in a 16-bit output field, and only updating those bits in the output register for which
the corresponding mask bit is set.
Offset: SIU_BASE + 0x0D04
Access: User read/write
0
1
2
3
4
5
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7
8
9
10
11
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13
14
15
R _{MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK}
W ^{15 14 13 12 11 10 9}
8
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3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
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31
R _{DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA}
W ^{15 14 13 12 11 10 9}
8
7
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4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-55. Masked Serial GPO Register for DSPI_A Low (SIU_DSPIAL)
Table 8-34. SIU_DSPIAL Field Descriptions
Field
Description
MASKn
DATAn
Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_A.
0 The previous value defined by GPO for DSPI_A is maintained.
1 The corresponding GPO for DSPI_A is written with the value defined by the DATAn field.
Pin Data Out. This bit stores the data to be driven out on the GPO for DSPI_A output controlled by this register.
0 Logic low value is driven for the corresponding GPO for DSPI_A when this output is selected in the DSPI
serialization module.
1 Logic high value is driven for the corresponding GPO for DSPI_A when this output is selected in the DSPI
serialization module.
8.3.2.48 Masked Serial GPO Register for DSPI_B High (SIU_DSPIBH)
The SIU_DSPIBH register allows any combination of bits in the top half of the 32-bit serialized data frame
from DSPI_B to be updated with a single 32-bit write operation, while allowing other bits to maintain their
previous state. This is accomplished by writing a 16-bit masked value coherently with an update value
contained in a 16-bit output field, and only updating those bits in the output register for which the
corresponding mask bit is set.
8-58
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor