PXN20RM Datasheet, PDF (857/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
MODE[6] = 0
EDPOL = 1
Direction (from UC[n])
Count (from UC[n – 1])
EMIOS_CCNTR[n] inc/dec
EMIOS_CCNTR[n]
+1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1
A1 Write
(Value 1)
A1 Match
A1 Match
Value 1
0x000000
FLAG Pin/Register
Time
Notes: EMIOS_CADR[n]  A1
Figure 28-31. Quadrature Decode Mode Example with Count & Direction Encoder
Phase A (from UC[n])
Phase B (from UC[n – 1])
EMIOS_CCNTR[n] inc/dec
EMIOS_CCNTR[n]
+1 +1 +1 +1 +1 +1 +1 [phone] +1 +1 +1 +1 +1 +1 +1 [phone] +1 +1 +1 +1 +1 +1 +1
A1 Write A1 Match
(Value 1)
A1 Match
A1 Match A1 Write A1 Match
(Value 2)
A1 Match
Value 2
Value 1
0x000000
FLAG Pin/Register
Notes: EMIOS_CADR[n] = A1
MODE[6] = 0
Time
Figure 28-32. Quadrature Decode Mode Example with Phase_A & Phase_B Encoder
28.4.1.1.10 Modulus Counter (MC) Mode
The MC mode can be used to provide a time base for a counter bus or as a general purpose timer.
MODE[6] bit selects internal or external clock source when cleared or set, respectively. When external
clock is selected, the input signal pin is used as the source and the triggering polarity edge is selected by
the EDPOL and EDSEL in the EMIOS_CCR[n] register.
The internal counter counts up from the current value until it matches the value in register A1. Register B1
is cleared and is not accessible to the MCU. The MODE[4] bit selects up mode or up/down mode, when
cleared or set, respectively.
When in up count mode, a match between the internal counter and register A1 sets the FLAG and clears
the internal counter. The timing of those events varies according to the MC mode setup as follows:
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
28-35