PXN20RM Datasheet, PDF (200/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Offset: SIU_BASE + 0x0018
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0000
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0000
0
0
0
0
0
0
0
0
0
0
16
17
18 19 20 21
22
R _{EIRE EIRE EIRE EIRE EIRE EIRE EIRE}
W ^{15 14 13 12 11 10 9}
Reset 0
0
0000
0
23
EIRE
8
0
24
EIRE
7
0
25
EIRE
6
0
26
EIRE
5
0
27
EIRE
4
0
28
EIRE
3
0
29
EIRE
2
0
30
EIRE
1
0
31
EIRE
0
0
Figure 8-6. SIU DMA/Interrupt Request Enable Register (SIU_DIRER)
Table 8-8. SIU_DIRER Field Descriptions
Field
Description
EIREn
External Interrupt Request Enable n. Enables assertion of the interrupt request from the SIU to the interrupt
controller when an edge triggered event occurs on the IRQn pin.
0 External interrupt request disabled.
1 External interrupt request enabled.
8.3.2.6 DMA/Interrupt Request Select Register (SIU_DIRSR)
The SIU_DIRSR allows selection between a DMA or interrupt request for events on the IRQ1–IRQ0
inputs. The SIU_DIRSR selects between DMA and interrupt requests. If the corresponding bits are set in
SIU_EISR and the SIU_DIRER, then the DMA/interrupt request select bit determines whether a DMA or
interrupt request is asserted.
Offset: SIU_BASE + 0x001C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
W
Reset 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
16
R0
W
Reset 0
17
18 19 20 21
22
23
24
25
26
27
28
0 0000 0
0
0
0
0
0
0
0 0000 0
0
0
0
0
0
0
Figure 8-7. DMA/Interrupt Request Select Register (SIU_DIRSR)
29
30
31
0
DIRS1 DIRS0
0
0
0
Table 8-9. SIU_DIRSR Field Descriptions
Field
Description
DIRSn
DMA/Interrupt Request Select n. Selects between a DMA or interrupt request when an edge triggered event occurs
on the corresponding IRQn pin.
0 Interrupt request selected.
1 DMA request selected.
8-18
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor