PXN20RM Datasheet, PDF (149/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Field
LVI5HF
LVI5NF
LVI5F
FRF
FRDY
Clocks, Reset, and Power (CRP)
Table 6-14. CRP_SOCSC Field Descriptions (continued)
Description
LVI 5V High Interrupt Flag. The LVI5HF bit indicates that the LVI5H LVI circuit has detected that the 5V supply
is below the trip limit. LVI5HF is cleared by writing a 1 to LVI5HF. Writing a 0 to LVI5HF has no effect.
0 No LVI5H interrupt.
1 LVI5H interrupt.
Note: The LVI5H LVI circuit is disabled when VRCSEL is low and thus LVI5HF remains cleared.
LVIN 5V Interrupt Flag. The LVI5NF bit indicates that the LVI5 LVI circuit has detected that the 5 V supply is
above the defined trip limit. LVI5NF is cleared by writing a 1 to LVI5NF. Writing a 0 to LVI5NF has no effect.
Note: If the supply remains above the defined trip limit, the LVI5NF flag is immediately re-set after the clear
sequence.
0 No LVI5 negation interrupt.
1 LVI5 negation interrupt.
Note: The LVI5 LVI circuit is disabled when VRCSEL is low and thus LVI5NF remains set.
LVI 5V Interrupt Flag. The LVI5F bit indicates that the LVI5 LVI circuit has detected that the 5 V supply is below
the defined trip limit. LVI5F is cleared by writing a 1 to LVI5F. Writing a 0 to LVI5F has no effect.
Note: If the supply remains below the defined trip limit, the LVI5F flag is immediately re-set after the clear
sequence.
0 No LVI5 assertion interrupt.
1 LVI5 assertion interrupt.
Note: The LVI5 LVI circuit is disabled when VRCSEL is low and thus LVI5F remains cleared.
Flash Ready Flag. The FRF bit is set when the Flash becomes available for read/write operations after
recovery from Sleep or reset. FRF is cleared by writing a 1 to FRF. Writing a 0 to FRF has no effect.
exiting low Power mode. It is used to notify the user software that Flash operation may begin.
0 Flash not ready.
1 Flash ready.
Flash Ready. The FRDY bit is a real time indication of whether the Flash is ready for read/write operations after
recovery from Sleep or reset.
0 Flash not ready.
1 Flash ready.
6.3 Functional Description
6.3.1 Low-Power Mode
The CRP supports a low power mode of operation, Sleep. During Sleep, the CRP logic remains powered
and is not reset. The standard cell logic is powered down in Sleep mode. In order to achieve the functional
requirements of this low power mode, the CRP provides the following functionality: control of the on-chip
voltage regulator, LVI circuits, and power gates; wakeup monitoring on external pins or internal RTC/API;
external reset pin monitoring to allow user to abort the low power mode; system recovery on wakeup; and
support for JTAG and Nexus debug capability. The following sections discuss in detail the entry sequence,
the operation, and the exit sequence for the low power Sleep mode.
6.3.2 Wake-Up Lines
The wake-up lines are implemented as described in Chapter 8, System Integration Unit (SIU), and detailed
in Section 6.2.2.5, Pin Wakeup Enable Registers (CRP_PWKENH/L). These wake-up signals generate an
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
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