PXN20RM Datasheet, PDF (1031/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
31.4.5.3.19 Parity Checking
The eSCI module calculates the parity of a received character and checks is versus the received parity bit
in the received data frame when the parity enable bit PE in the eSCI Control Register 1 (eSCI_CR1) is set.
The parity type bit PT in the eSCI Control Register 1 (eSCI_CR1) defines whether to check for odd or even
parity is generated. If an parity error is detected, this is reported as described in Section 31.4.5.4, Reception
Error Reporting.
31.4.5.4 Reception Error Reporting
The receiver can detect four error types: parity errors, framing errors, noise errors, and the overrun error.
The receiver reports the errors detected during frame reception at the end of the reception of the last stop
bit of a frame. For error reporting the receiver utilizes the OR, NF, FE, and PF flags in the eSCI Interrupt
Flag and Status Register 1 (eSCI_IFSR1).
If the receiver has detected an overrun as described in Section 31.4.5.3.11, Receiver Overrun, only the OR
flag is set. All other error flags are not updated.
If the receiver has not detected an overrun and has detected noise as described in Section 31.4.5.3.13, Bit
Sampling, the NF flag is set.
If the receiver has not detected an overrun and has detected a framing error as described in
Section 31.4.5.3.13, Bit Sampling, the FE flag is set.
If the receiver has not detected an overrun and has detected a parity error as described in
Section 31.4.5.3.19, Parity Checking, the PF flag is set.
31.4.5.5 Multiprocessor Communication
The multiprocessor communication allows one processor to send blocks of frames to other processors on
the same serial link. To avoid the received data interrupt for frames not intended for the processor, the eSCI
receiver can be put into the wakeup state. If the receiver is in the wakeup state, the eSCI still loads the
received data into the eSCI SCI Data Register (eSCI_SDR), but does not set the RDRF flag and
consequently does not request the RDRF interrupt.
The receiver leaves the wakeup state and clears the RWU bit in the eSCI Control Register 1 (eSCI_CR1)
when the wakeup pattern configured by WAKE bit in eSCI Control Register 1 (eSCI_CR1) is received.
The eSCI module supports two types of wakeup patterns, the idle-line wakeup pattern and the
address-mark wakeup pattern.
31.4.5.5.1 Idle-Line Wakeup
The idle-line wakeup mode is selected when the WAKE bit in eSCI Control Register 1 (eSCI_CR1) is 0.
In this mode, the receiver leaves the wakeup state, when an idle character is detected as described in
Section 31.4.5.3.8, Idle Character Detection. The next received frame is the address frame, which contains
address information that can be evaluated by the application. If the application decides not to receive the
frame block, it can set the RWU bit in the eSCI Control Register 1 (eSCI_CR1) and return the receiver to
the wakeup state.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
31-41