PXN20RM Datasheet, PDF (963/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
Control
Logic
Slave Bus Interface
Shift Register
SIN
0 1 • • • • • N–1
N
DSI Deserialization N Parallel
Data Register
Outputs
In TSB configuration, the number of bits N = 32. For non-TSB, N = 16.
Figure 30-22. DSI Deserialization Diagram
30.4.4.5 DSI Transfer Initiation Control
Data transfers for a master DSPI in DSI configuration are initiated by a condition. The transfer initiation
conditions are selected by the TRRE and CID bits in the DSPI_DSICR. Table 30-25 lists the transfer
initiation conditions.
Table 30-25. DSI Data Transfer Initiation Control
DSPI_DSICR Bits
TRRE
CID
0
0
0
1
Transfer Initiation Control
Continuous
Change in Data
30.4.4.5.1 Continuous Control
For continuous control, the initiation of a transfer is based on the baud rate at which data is transferred
between the DSPI and the external device. The baud rate is set in the DSPI_CTARn register selected by
the DSICTAS field in the DSPI_DSICR. A new DSI frame shifts out when the previous transfer cycle has
completed and the delay after transfer (t_DT) has elapsed.
30.4.4.5.2 Change In Data Control
For change in data control, a transfer is initiated when the data to be serialized has changed since the
transfer of the last DSI frame. A copy of the previously transferred DSI data is stored in the
DSPI_COMPR. When the data in the DSPI_SDR or the DSPI_ASDR is different from the data in the
DSPI_COMPR, a new DSI frame is transmitted. The TXSS bit in the DSPI_DSICR selects the register to
which the DSPI_COMPR is compared.
30.4.5 Combined Serial Interface (CSI) Configuration
The CSI configuration of the DSPI is used to support SPI and DSI functions on a frame by frame basis.
CSI configuration allows interleaving of DSI data frames from the parallel input signals with SPI
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
30-37