PXN20RM Datasheet, PDF (275/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
IVPR
0
Vector base
+
Hardware Vector Mode Offset
0
0x0_0000
=
Hardware Vector Mode Interrupt Exception Handler Address
0
Vector base
19 20
0x000
19 20 21
29
0b1
Vector
19 20 21
29
0b1
Vector
31
30
31
0b00
30
31
0b00
Figure 10-7. Z0 Hardware Vector Mode: Interrupt Exception Handler Address Calculation
IVPR
0
+ Hardware vector
mode offset
0
= Interrupt exception
handler address
0
PREFIX
0x0000
PREFIX
15 16
31
0x0000
15 16 18 19
27 28
31
0b000 INTC_IACKR[INTVEC]
0b0000
15 16 18 19
27 28
31
0b000 IRQ SPECIFIC OFFSET 0b0000
Figure 10-8. Z6 Hardware Vector Mode: Interrupt Exception Handler Address Calculation
The processor negates INTC’s interrupt request when automatically acknowledging the interrupt request.
However, the interrupt request to the processor do not negate if a higher priority interrupt request arrives.
Even in this case, the interrupt vector number does not update to the higher priority request until the lower
priority request is acknowledged by the processor.
The assertion of the interrupt acknowledge signal pushes the PRI value in the INTC_CPR_PRCn onto the
LIFO and updates PRI in the INTC_CPR_PRCn with the new priority.
10.2 External Signal Description
The INTC has no direct external MCU signals. However, there are external pins that can be configured in
the SIU as external interrupt request input pins. When configured in this function, an interrupt on the pin
sets an external interrupt flag. These flags can cause one of five peripheral interrupt requests to the
interrupt controller.
For more information on external interrupts, the pins used, and how to configure them, refer to Chapter 3,
Signal Description, and Chapter 8, System Integration Unit (SIU), for more information on these pins.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
10-7