PXN20RM Datasheet, PDF (610/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
the data DMA is complete and the buffer descriptor status bits have been written by the DMA engine, the
RxBD[E] or TxBD[R] bit is cleared by hardware to signal that the buffer has been “consumed.” Software
may poll the BDs to detect when the buffers have been consumed or may rely on the buffer/frame
interrupts. These buffers may then be processed by the driver and returned to the free list.
The ECR[ETHER_EN] signal operates as a reset to the BD/DMA logic. When ECR[ETHER_EN] is
deasserted the DMA engine BD pointers are reset to point to the starting transmit and receive BDs. The
buffer descriptors are not initialized by hardware during reset. At least one transmit and receive buffer
descriptor must be initialized by software before the ECR[ETHER_EN] bit is set.
The buffer descriptors operate as two separate rings. ERDSR defines the starting address for receive BDs
and ETDSR defines the starting address for transmit BDs. The last buffer descriptor in each ring is defined
by the wrap (W) bit. When set, W indicates that the next descriptor in the ring is at the location pointed to
by ERDSR and ETDSR for the receive and transmit rings, respectively. Buffer descriptor rings must start
on a 32-bit boundary; however, it is recommended they are made 128-bit aligned.
25.5.1.1 Driver/DMA Operation with Transmit BDs
Typically a transmit frame is divided between multiple buffers. An example is to have an application
payload in one buffer, TCP header in a second buffer, IP header in a third buffer, Ethernet/IEEE 802.3
header in a fourth buffer. The Ethernet MAC does not prepend the Ethernet header (destination address,
source address, length/type fields), so this must be provided by the driver in one of the transmit buffers.
The Ethernet MAC can append the Ethernet CRC to the frame. Whether the CRC is appended by the MAC
or by the driver is determined by the TC bit in the transmit BD which must be set by the driver.
The driver (TxBD software producer) should set up Tx BDs in such a way that a complete transmit frame
is given to the hardware at once. If a transmit frame consists of three buffers, the BDs should be initialized
with pointer, length and control (W, L, TC, ABC) and then the TxBD[R] bits should be set = 1 in reverse
order (3rd, 2nd, 1st BD) to ensure that the complete frame is ready in memory before the DMA begins. If
the TxBDs are set up in order, the DMA Controller could DMA the first BD before the 2nd was made
available, potentially causing a transmit FIFO underrun.
In the FEC, the DMA is notified by the driver that new transmit frames are available by writing to the
TDAR register. When this register is written to (data value is not significant) the FEC RISC tells the DMA
to read the next transmit BD in the ring. Once started, the RISC + DMA continues to read and interpret
transmit BDs in order and DMA the associated buffers, until a transmit BD is encountered with the R
bit = 0. At this point, the FEC polls this BD one more time. If the R bit = 0 the second time, then the RISC
stops the transmit descriptor read process until software sets up another transmit frame and writes to
TDAR.
When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the R bit,
indicating that the hardware consumer is finished with the buffer.
25.5.1.2 Driver/DMA Operation with Receive BDs
Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore the
driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to
the EMRBR register.
25-44
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor