PXN20RM Datasheet, PDF (966/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
30.4.6 Buffered SPI Operation
The DSPI can use a FIFO buffering mechanism to transmit and receive commands and data to and from
external devices. The transmit FIFO buffers SPI commands and data to be transferred. The receive FIFO
buffers incoming serial data. Both FIFOs are four entries deep. The TX FIFO stores 32-bit words when the
DSPIs are configured for master mode. The 32-bit words are composed of 16-bit command fields and data
fields as wide as 16 bits. The RX FIFOs store 16-bit words of received data from external devices. When
the DSPI is configured for slave mode, the DSPI ignores the SPI command in the TX FIFO.
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers
between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or
through host software. See Figure 30-26 for conceptual diagram of the queue data transfer control in the
MCU.
System RAM
Address
RX queue
TX queue
Data
Data
DMA controller/
host
Data
DSPI
Data
Address
DMA
control/
host
TX FIFO RX FIFO
Shift register
Figure 30-26. DSPI Queue Transfer Control in PXN20
30.4.7 DSPI Baud Rate and Clock Delay Generation
The SCK frequency and the delay values for serial transfer are generated by dividing the system clock
frequency by a prescaler and a scaler with the option for doubling the baud rate. Figure 30-27 shows
conceptually how the SCK signal is generated.
System clock
1
Prescaler
1 + DBR
Scaler
SCK
Figure 30-27. Communications Clock Prescalers and Scalers
30.4.7.1 Baud Rate Generator
The baud rate is the frequency of the serial communication clock (SCK). The system clock is divided by
a baud rate prescaler (defined by DSPI_CTARn[PBR]) and baud rate scaler (defined by
30-40
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor