PXN20RM Datasheet, PDF (1374/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Memory Map
Table A-5. e200z6 Core SPR Numbers (Supervisor Mode) (continued)
Register
MAS3
MAS4
MAS6
PID0
MMUCSR0
MMUCFG
TLB0CFG
TLB1CFG
L1CFG0
L1CSR0
L1FINV0
SPEFSCR
Description
MMU Assist Register 3
MMU Assist Register 4
MMU Assist Register 6
Process ID Register
MMU Control and Status Register 0
MMU Configuration Register
TLB 0 Configuration Register
TLB 1 Configuration Register
Cache Registers
L1 Cache Configuration Register
L1 Cache Control and Status Register 0
L1 Cache Flush and Invalidate Control Register 0
APU Registers
SPE APU Status and Control Register
SPR (decimal)
627
628
630
48
1012
1015
688
689
515
1010
1016
512
Table A-6. e200z6 Core SPR Numbers (User Mode)
Register
Description
General Registers
CTR
Count Register
LR
Link Register
XER
Integer Exception Register
GPR0–GPR31 General Purpose Registers
Special Purpose Registers
SPRG4
Special Purpose Register 4
SPRG5
Special Purpose Register 5
SPRG6
Special Purpose Register 6
SPRG7
Special Purpose Register 7
USPRG0 User Special Purpose Register
Timer Registers
TBL
Time Base Lower Register
TBU
Time Base Upper Register
Cache Registers
L1CFG0 L1 Cache Configuration Register
SPR (decimal)
9
8
1
N/A
260
261
262
263
256
268
269
515
A-116
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor