PXN20RM Datasheet, PDF (1182/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Table 36-19. Nexus3+ Memory Map (continued)
Access
Opcode
0xB
0xD
0xE
0xF
0x12
0x13
0x14 -> 0x3F
Register Name
WT
DTC
DTSA1
DTSA2
DTEA1
DTEA2
—
Register Description
Watchpoint trigger
Data trace control
Data trace start address 1
Data trace start address 2
Data trace end address 1
Data trace end address 2
Reserved
Read Address Write Address
0x16
0x1A
0x1C
0x1E
0x24
0x26
0x28->0x7E
0x17
0x1B
0x1D
0x1F
0x25
0x27
0x29->0x7F
36.6.8 Nexus3+ Register Definition
36.6.8.1 Development Control Register 1, 2 (DC1, DC2)
The development control registers are used to control the basic development features of the Nexus module.
Figure 36-14 shows DC1 and Table 36-20 describes the register’s fields.
Nexus Reg: 0x02
31
R OPC
W
Reset 0
30
29
MCK_DIV
0
0
28
27
EOC
0
0
Access: User read/write
26
25
24
23
22
21
20
19
18
17
16
0
00000000
PTM WEN
0
0
0
00000000
15
14
13
12
11
10
9
8
7
6
5
4
3
R0
0
0
0
0
0
0
0
OVC
EIC
W
Reset 0
0
0
0
0
0
0
0
00000
Figure 36-14. Development Control Register 1 (DC1)
Table 36-20. DC1 Field Descriptions
Field
OPC¹
MCK_DIV¹
Description
Output Port Mode Control.
0 Reduced-port mode configuration (4 MDO pins).
1 Full-port mode configuration (8 MDO pins).
MCKO Clock Divide Ratio (see note below).
00 MCKO is 1x processor clock freq.
01 MCKO is 1/2x processor clock freq.
10 MCKO is 1/4x processor clock freq.
11 MCKO is 1/8x processor clock freq.
2
1
0
TM
000
36-32
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor