PXN20RM Datasheet, PDF (960/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
The DSPI ignores attempts to push data to a full TX FIFO, i.e., the state of the TX FIFO is unchanged. No
error condition is indicated.
30.4.3.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO counter
is decremented by one. At the end of a transfer, the TCF bit in the DSPI_SR is set to indicate the
completion of a transfer. The TX FIFO is flushed by writing a ‘1’ to the CLR_TXF bit in DSPI_MCR.
If an external bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is empty,
the Transmit FIFO Underflow Flag (TFUF) in the slave’s DSPI_SR is set. See Section 30.4.12.4, Transmit
FIFO Underflow Interrupt Request (TFUF), for details.
30.4.3.5 Receive First-In First-Out (RX FIFO) Buffering Mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds four received
SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the received data
in the shift register is transferred into the RX FIFO. SPI data are removed (popped) from the RX FIFO by
reading the DSPI POP RX FIFO Register (DSPI_POPR). RX FIFO entries can only be removed from the
RX FIFO by reading the DSPI_POPR or by flushing the RX FIFO. For more information on the
DSPI_POPR, refer to Section 30.3.2.7, DSPI POP RX FIFO Register (DSPI_POPR).
The RX FIFO Counter field (RXCTR) in the DSPI Status Register (DSPI_SR) indicates the number of
valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is
copied from the shift register to the RX FIFO.
The POPNXTPTR field in the DSPI_SR points to the RX FIFO entry that is returned when the
DSPI_POPR is read. The POPNXTPTR contains the positive offset from DSPI_RXFR0 in number of
32-bit registers. For example, POPNXTPTR = 0b0010 means that the DSPI_RXFR2 contains the received
SPI data that is returned when DSPI_POPR is read. The POPNXTPTR field is incremented every time the
DSPI_POPR is read.
30.4.3.5.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time a SPI frame is transferred to
the RX FIFO, the RX FIFO counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPI_SR is asserted
indicating an overflow condition. Depending on the state of the ROOE bit in the DSPI_MCR, the data from
the transfer that generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit
is asserted, the incoming data is shifted in to the shift register. If the ROOE bit is negated, the incoming
data is ignored.
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor