PXN20RM Datasheet, PDF (576/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
Table 25-3. MIB Counters Memory Map (continued)
Offset from
FEC_BASE
(0xFFF4_C000)¹
Mnemonic
Description
0x02D0
IEEE_R_CRC
Frames Received with CRC Error
0x02D4
IEEE_R_ALIGN
Frames Received with Alignment Error
0x02D8
IEEE_R_MACERR
Receive Fifo Overflow count
0x02DC
IEEE_R_FDXFC
Flow Control Pause frames received
0x02E0
IEEE_R_OCTETS_OK
Octet count for Frames Rcvd w/o Error
1 _{All accesses to and from the FEC memory map must be via 32-bit accesses. There is no support for}
accesses other than 32-bit.
25.3.4 Registers
25.3.4.1 FEC Burst Optimization Master Control Register (FBOMCR)
Although not an FEC register, the FEC burst optimization master control register (FBOMCR) controls
FEC burst optimization behavior on the system bus, hence it is mentioned here. Full details are provided
in Section 19.2.2.1, FEC Burst Optimization Master Control Register (FBOMCR). FEC registers are
described in Section 25.3.4.21, FIFO Receive Start Register (FRSR), through Section 25.3.4.24, Receive
Buffer Size Register (EMRBR).
In order to increase throughput, the FEC interface to the system bus can accumulate read requests or writes
to burst those transfers on the system bus. The FBOMCR determines the XBAR ports for which this
bursting is enabled, as well as whether the bursting is for reads, writes, or both. FBOMCR also controls
how errors for writes are handled. The FBOMCR address is 0xFFF4_0024, which is the ECSM base
address 0xFFF4_0000 plus the offset of 0x0024.
25.3.4.2 Ethernet Interrupt Event Register (EIR)
When an event occurs that sets a bit in the EIR, an interrupt is generated if the corresponding bit in the
interrupt mask register (EIMR) is also set. The bit in the EIR is cleared if a one is written to that bit
position; writing zero has no effect. This register is cleared on hardware reset.
These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and
internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB,
and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR,
BABR, BABT, LC, and RL. Interrupts resulting from internal errors are HBERR and UN.
Some of the error interrupts are independently counted in the MIB block counters. Software may choose
to mask off these interrupts, since these errors are visible to network management via the MIB counters:
• HBERR – IEEE_T_SQE
• BABR – RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)
• BABT – RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)
25-10
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor