PXN20RM Datasheet, PDF (841/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
28.3.2.9 eMIOS200 Status Register (EMIOS_CSR[n])
Offset: UC[n] base address + 0x0010
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R OVR 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
R OVFL 0
W w1c
Reset 0
0
18
19
20
21
22
23
24
25
26
27
28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 28-11. eMIOS200 Status Register (EMIOS_CSR[n])
29
30
31
UCIN UCOUT FLAG
w1c
0
0
0
Table 28-12. EMIOS_CSR[n] Field Descriptions
Field
OVR
OVFL
UCIN
UCOUT
FLAG
Description
Overrun Bit. The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set. This
bit can be cleared by clearing the FLAG bit or by software writing a 1.
0 Overrun has not occurred.
1 Overrun has occurred.
Overflow Bit. The OVFL bit indicates that an overflow has occurred in the internal counter. This bit must be
cleared by software writing a 1.
0 An overflow has not occurred.
1 An overflow has occurred.
Unified Channel Input Pin Bit. The UCIN bit reflects the input pin state after being filtered and synchronized.
Unified Channel Output. The UCOUT bit reflects the output pin state.
FLAG Bit. The FLAG bit is set when an input capture or a match event in the comparators occurred. This bit
must be cleared by software writing a 1.
0 FLAG cleared.
1 FLAG set event has occurred.
Note: emios_flag_out reflects the FLAG bit value. When the DMA bit is set, the FLAG bit can be cleared by
the DMA controller.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
28-19