PXN20RM Datasheet, PDF (847/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
EDSEL = 1
EDPOL = x
Update to
A1
A1 Match
A1 Match
A1 Match
Output
Flip-Flop
Selected
Counter Bus
0x000500
0x001000
0x001100
0x001000
0x001100
FLAG
Set Event
A1 Value^{1 0xxxxxxx 0x001000 0x001000}
0x001000
Note: ¹ EMIOS_CADR[n] = A2
Figure 28-18. SAOC Example —Toggling the Output Flip-Flop
0x001000
0x001000
EDSEL = 1
EDPOL = x
Output Flip-Flop
Selected Counter Bus
0x0
0x1
0x2
0x3
0x1
0x2
0x0
0x1
0x2
System Clock
A1 Match
FLAG Set Event
FLAG Pin/Register
FLAG Clear
A2 Value1 0x1
Note: ¹ EMIOS_CADR[n]  A2
Figure 19. SAOC Example with Flag Behavior
28.4.1.1.4 Input Pulse-Width Measurement (IPWM) Mode
The IPWM mode (MODE = 000_0100) allows the measurement of the width of a positive or negative
pulse by capturing the leading edge on register B1 and the trailing edge on register A2. Successive captures
are done on consecutive edges of opposite polarity. The leading edge sensitivity (i.e., pulse polarity) is
selected by EDPOL bit in the EMIOS_CCR[n] register. Registers EMIOS_CADR[n] and
EMIOS_CBDR[n] return the values in register A2 and B1, respectively.
The capture function of register A2 remains disabled until the first leading edge triggers the first input
capture on register B2. When this leading edge is detected, the count value of the selected time base is
latched into register B2; the FLAG bit is not set. When the trailing edge is detected, the count value of the
selected time base is latched into register A2 and, at the same time, the FLAG bit is set and the content of
register B2 is transferred to register B1 and to register A1.
If subsequent input capture events occur while the corresponding FLAG bit is set, registers A2, B1, and
A1 are updated with the latest captured values and the FLAG remains set. Registers EMIOS_CADR[n]
and EMIOS_CBDR[n] return the value in registers A2 and B1, respectively.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
28-25