PXN20RM Datasheet, PDF (1095/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
Table 34-8. IMR Field Descriptions (continued)
Field
Description
MSKEOCTU Mask bit for End of CTU Conversion interrupt (EOCTU). When set, the EOCTU interrupt is enabled.
MSKJEOC Mask bit for End of Injected Channel Conversion interrupt (JEOC). When set, the JEOC interrupt is enabled.
MSKJECH Mask bit for End of Injected Chain Conversion interrupt (JECH). When set, the JECH interrupt is enabled.
MSKEOC Mask bit for End of Channel Conversion interrupt (EOC). When set, the EOC interrupt is enabled.
MSKECH Mask bit for End of Chain Conversion interrupt (ECH). When set, the ECH interrupt is enabled.
34.3.2.8 Channel Interrupt Mask Register 0 (CIMR0)
The CIMR0 register contains the Channel Interrupt Enable bits for group 0 channels (channels 0–31).
Address: ADC_BASE + 0x0024
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R _{CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM}
W ^{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _{CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM CIM}
W ^{15 14 13 12 11 10 9}
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34-9. Channel Pending Register 0 (CIMR0)
Table 34-9. CIMR0 Field Descriptions
Field
CIMn
Description
When set, the interrupt for channel n is enabled.
34.3.2.9 Channel Interrupt Mask Register 1 (CIMR1)
The CIMR1 register contains the Channel Interrupt Enable bits for group 1 channels (channels 32–63).
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
34-15