PXN20RM Datasheet, PDF (470/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Error Correction Status Module (ECSM)
Offset: ECSM_BASE_ADDR + 0x0050
Access: User read-only
0
R
W
Reset U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PFEAR
U
U
U
U
U
U
U
U
UU U
U
U
U
U
16
R
W
Reset U
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PFEAR
U
U
U
U
U
U
U
U
UU U
U
U
U
U
Figure 19-5. Platform Flash ECC Address (PFEAR) Register
Table 19-7. PFEAR Field Descriptions
Field
Description
PFEAR Platform Flash ECC Address Register. Contains the faulting access address of the last properly enabled platform
flash ECC event.
19.2.2.6 Platform Flash ECC Master Number Register (PFEMR)
The PFEMR is a 4-bit register for capturing the AXBS bus master number of the last properly enabled
ECC event in the platform flash memory. Depending on the state of the ECC configuration register, an
ECC event in the platform flash causes the address, attributes and data associated with the access to be
loaded into the PFEAR, PFEMR, PFEAT, and PFEDR registers and also the appropriate flag (PF1BC or
PFNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See Figure 19-6 and Table 19-8 for the platform
flash ECC master number register definition.
Offset: ECSM_BASE_ADDR + 0x0056
Access: User read-only
0
1
2
3
4
5
6
7
R
0
0
0
0
PFEMR
W
Reset
0
0
0
0
U
U
U
U
Figure 19-6. Platform Flash ECC Master Number (PFEMR) Register
Table 19-8. PFEMR Field Descriptions
Field
Description
PFEMR Platform Flash CC Master Number Register. Contains the AXBS bus master number of the faulting access of the
last properly enabled platform flash ECC event.
19.2.2.7 Platform Flash ECC Attributes Register (PFEAT)
The PFEAT is an 8-bit register for capturing the AXBS bus master attributes of the last properly enabled
ECC event in the platform flash memory. Depending on the state of the ECC configuration register, an
19-10
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor