PXN20RM Datasheet, PDF (808/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Isochronous/Synchronous Data Buffering Examples
(Shows RX/TX handling of Isochronous/Synchronous Data using the Current Buffer)
Note 1
BSA
BCA
Note 3
BCA
Isochronous
Packet 1
(First Packet)
Isochronous
Packet 2
Synchronous
Data
Isochronous
Packet 3
Note 2
BS
Legend
= 16-bit address pointer
= channel interrupt
BEA
BFA
Isochronous
Packet N
(Last Packet)
BD
Current Buffer Current Buffer
for Synchronous for Isochronous
channel
channel
Figure 27-20. Isochronous/Synchronous Data Buffering Examples
Note 4
For reception or transmission of isochronous data, single-packet and multi-packet buffering is handled in
the same manner. Since isochronous channels have a fixed packet length (determined by CECRn[IPL]),
software should set the system memory buffer length as an even multiple of CECRn[IPL] for multi-packet
buffering and equal to CECRn[IPL] for single-packet buffering. It is assumed that all isochronous packets
in the system are of the same length, with the minimum supported length being 5 bytes.
For reception or transmission of synchronous data, the concept of multi-packet or single-packet buffering
is not applicable since synchronous data has no packet format. As a result, CCBCRn[BFA] always
indicates the end address of the Current Buffer for synchronous channels.
27.4.7 DMA Controller (Circular Buffering)
Logical channels can be programmed to operate using circular buffering by programming
CECRn[MDS[1:0]] = 01. It is recommended that circular buffering be used with synchronous channels
only (CECRn[CT[1:0]] = 00). Logical channels configured for transmitting or receiving other types of
data (e.g. asynchronous, control, or isochronous) should not use circular buffering.
In contrast ping-pong buffering, this mode effectively uses a single, circular system memory buffer to
process channel data. Software must program the beginning and ending address of the circular buffer in
the CNBCRn[BSA] and CNBCRn[BEA] fields. For proper operation, software must not change the
addresses in CNBCRn[BSA] and CNBCRn[BEA] once buffer processing has started.
27-36
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor