PXN20RM Datasheet, PDF (205/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
• If the pin is configured as an input, the ODE and SRC bits do not apply.
• If the pin is configured as an output, the HYS bit does not apply.
• When a pin is configured as an output, the weak internal pull up/down is disabled, regardless of the
WPE or WPS settings in the SIU_PCR.
IBE and OBE bit definitions are specific to each SIU_PCR. When an I/O function is input- or output-only,
the IBE and OBE bits do not have to be set to enable the input or output. When an I/O function can be
either an input and output, the IBE and OBE bits must be set accordingly (IBE = 1 for input, and OBE = 1
for output). For I/O functions that change direction dynamically, such as the MLBSIG and MLBDAT,
switching between input and output is handled internally, and the IBE and OBE bits have no effect.
For all SIU_PCRs where GPIO function is available on the pin, if the pin is configured as an output and
the IBE bit is set, the actual pin value is reflected in the corresponding GPDIn register. Negating the IBE
bit when the pin is configured as an output reduces noise and power consumption. Reads from the GPDIn
registers are undefined when the corresponding IBE bit is negated.
The SIU_PCRs are 16-bit registers that may be read or written as 32-bit values aligned on 32-bit address
boundaries. Table 8-16 describes the SIU_PCR fields.
NOTE
Not all of the fields may be present in a given SIU_PCR, depending on the
type of pad it controls. See the specific SIU_PCR definition.
For all SIU_PCRs, the associated pin supports GPIO and as many as three alternate functions. The PA field
is defined in Table 8-16. For all SIU_PCRs of this type, a value of 0b11 selects Function 3, a value of 0b10
selects Function 2, the value 0b01 selects Function 1, and a value 0b00 selects GPIO.
All pins are named according to their associated parallel port name and associated bit number. For
example, the Port A pins are named PA0 to PA15 (these pin names should not be confused with the PA
bitfield, which is present in every SIU_PCR.) See Table 3-1 in Section 3.4, Detailed Signal Description,
for a list of pins and their functions, including values for the PA bitfield for setting the function of each
GPIO pin.
NOTE
Table 3-1 lists the available functions for each pin. Do not select reserved
values for the PA bitfield.
Some SIU_PCRs contain a slew rate control (SRC) field. Slew rate control pertains to pins with slow or
medium I/O pad types. The SRC field for all SIU_PCRs with slew rate control is defined in Table 8-16.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-23