PXN20RM Datasheet, PDF (272/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
IRQs
Interrupt
controller
(INTC)
External interrupt
exception request
e200z6
or
e200z0
core
Figure 10-2. INTC Software Vector Mode
Typical program flow for software vector mode is shown in Figure 10-3.
IRQ[n]
taken
Address
IVPR + IVOR4
Instructions Address
Prolog
(Including
using IACKR
to get vector
then bl ISR_n
VTBA
IACKR
Epilog
Instructions
ISR 0 address
ISR 1 address
•••
ISR n address
•••
ISR N – 1 address
ISR 0
ISR
ISR 1
ISR
•••
ISR n
ISR
•••
ISR N – 1
ISR
N is the maximum number of usable interrupt vectors, which equals 316, and includes 26 reserved IRQ vectors
and eight software-settable IRQ vectors.
Figure 10-3. Program Flow–Software Vector Mode
The common interrupt exception handler address is calculated by hardware as shown in Figure 10-4 for
the Z0 core and Figure 10-5 for the Z6 core. The upper half of the interrupt vector prefix register (IVPR)
is added to the offset contained in the external input interrupt vector offset register (IVOR4).
NOTE
Since bits IVOR4[28:31] are not part of the offset value for the Z6, the
vector offset must be located on a quad-word (16-byte) aligned location in
memory. For the Z0 core, the value of IVOR4 is hard coded to 0x040.
10-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor