PXN20RM Datasheet, PDF (925/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
NOT_RDY bits in the CANx_MCR are set. The CNTX pin is in recessive state and FlexCAN does not
initiate frame transmission nor receives any frames from the CAN bus. Note that the message buffer
contents are not affected by reset, so they are not automatically initialized.
For any configuration change/initialization, it is required that FlexCAN is put into freeze mode (see
Section 29.4.8.1, Freeze Mode). The following is a generic initialization sequence applicable for the
FlexCAN module:
• Initialize the CANx_MCR
— Enable the individual filtering per MB and reception queue features by setting the BCC bit
— Enable the warning interrupts by setting the WRN_EN bit
— If required, disable frame self reception by setting the SRX_DIS bit
— Enable the FIFO by setting the FEN bit
— Enable the abort mechanism by setting the AEN bit
— Enable the local priority feature by setting the LPRIO_EN bit
• Initialize CANx_CTRL.
— Determine bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW.
— Determine the bit rate by programming the PRESDIV field.
— Determine internal arbitration mode (LBUF bit).
• Initialize message buffers.
— The control and status word of all message buffers must be initialized
— If FIFO was enabled, the 8-entry ID table must be initialized
— Other entries in each message buffer should be initialized as required
• Initialize the Rx individual mask registers
• Set required interrupt mask bits in the IMASK registers (for all MB interrupts), in CANx_CTRL
(for bus off and error interrupts) and in CANx_MCR for wake-up interrupt
• Negate the HALT bit in CANx_MCR
Starting with this last event, FlexCAN attempts to synchronize with the CAN bus.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
29-41