PXN20RM Datasheet, PDF (805/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Multi-Packet Buffering Example
(Shows RX/TX handling of Asynchronous/Control Packets using the Current Buffer)
BSA
BCA
Packet 1
(First Packet)
Note 2
BS
Note 3 _{internal register}
* RX handling only
Note 1
Note 4
BCA
Packet 2
Legend
= 16-bit address pointer
Packet 3
0
= channel interrupt
Note 5A
* RX handling only
BEA
BFA
Packet N
(Last Packet)
Note 5B
* TX handling only
BEA
BFA
Note 6
BD
Figure 27-19. Asynchronous/Control Packet Buffering Example
27.4.6.1.1 Packet Reception
When multi-packet buffering is used for receiving asynchronous or control data packets, buffer processing
should be handled in the following manner:
• At the start of buffer processing, the beginning of the Next Buffer becomes the beginning of the
Current Buffer, as CNBCRn[BSA] is loaded into CCBCRn[BCA]. Additionally, the end of the
Next Buffer becomes the end of the Current Buffer, as CNBCRn[BEA] is loaded into
CCBCRn[BFA] (See Note 1 in Figure 27-19).
• A Buffer Start interrupt is generated (CSCRn[STS[3]] set), which informs software that hardware
has updated CCBCRn, cleared the local channel CSCRn[RDY] bit, and is available to accept the
next buffer. Software may then prepare the Next Buffer by writing CNBCRn[BSA],
CNBCRn[BEA], and CSCRn[RDY]. (See Note 2 in Figure 27-19).
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
27-33