PXN20RM Datasheet, PDF (864/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
Write to A2
Cycle n
Cycle n + 1
System Clock
Prescaler
EMIOS_CCNTR
1
A1 Value 0x000004
A2 Value
B1 Value 0x000008
A1 Match
A1 Match Posedge
Detection
A1 Match Negedge
Detection
4
5
0x000000
A1 Match
Negedge
Detection
1
0x000000
Time
A1 Match Posedge Detection
B1 Match
B1 Match Negedge
Detection
Output Pin
EDPOL = 0
B1 Match Negedge Detection
No Transition at this Point
Figure 28-40. OPWFMB Mode with A1 = 0 (0% duty cycle)
Figure 28-41 shows the timing for the A1 and B1 registers load. The A1 and B1 load use the same signal
that is generated based on the selected counter reaching the value one, or EMIOS_CCNTR[n] = 1. This
event is defined as the cycle boundary. The load signal pulse has the duration of one system clock cycle
and occurs at the first system clock period of every counter cycle. If A2 and B2 are written within cycle
(n), their values are loaded into A1 and B1, respectively, at the first clock of cycle (n + 1) and the new
values are used for matches at cycle (n + 1). The update disable bits (OU[n] in EMIOS_OUDR) can be
used to control the update of these registers, thus allowing to delay the A1 and B1 registers update for
synchronization purposes.
In Figure 28-41, it is assumed that the channel and global prescalers are set to one, meaning that the
channel internal counter transition at every system clock cycle. FLAGs can be generated only on B1
matches when MODE[5] is cleared, or on either A1 or B1 matches when MODE[5] is set. Because B1
FLAG occurs at the cycle boundary, this flag can be used to indicate that A2 or B2 data written on cycle
(n) were loaded to A1 or B1, respectively, thus generating matches in cycle (n + 1).
28-42
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor