PXN20RM Datasheet, PDF (315/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
load INTC_IACKR_PRCn
if stacked PRI values are not depleted, branch to push_lifo
NOTE
Reading the INTC_IACKR_PRCn acknowledges the interrupt request to
the processor and updates the INTC_CPR_PRCn[PRI] with the priority of
the preempting interrupt request. If the processor recognition of interrupts is
disabled during the LIFO restoration, interrupt requests to the processor can
go undetected. However, since the peripheral or software settable interrupt
requests are not cleared, the peripheral interrupt request to the processor
re-asserts when INTC_CPR_PRCn[PRI] is lower than the priorities of those
peripheral or software settable interrupt requests.
10.6 Non-Maskable Interrupt (NMI)
The PXN20 can be configured to use the PC6 and PC5 pins as non-maskable interrupts (NMI) by
providing a path to the critical interrupt input of the e200z6 and e200z0 cores, respectively.
After the SIU is configured by user code, an NMI cannot be prevented from reaching the assigned core.
The only possible way of disabling the critical interrupt is by clearing the critical interrupt enable (CE) bit
in the core’s machine state register (MSR). The NMI has a higher priority than any interrupt request
generated by the INTC, and is not blocked or preempted by any other INTC interrupt request.
After the SIU is properly configured, the operation of the NMI always generates an interrupt request when
the programmed edge transition occurs on the pin, regardless of the selected muxing on that pin. It is the
user’s responsibility to assign pin multiplexing correctly for use with an NMI, which would normally mean
selecting it as a port pin rather than a peripheral function.
Figure 10-23 shows the various system level connections needed to create the NMI.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
10-47