PXN20RM Datasheet, PDF (1181/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Table 36-17. Event Code Encoding (TCODE = 33)
Event Code
Description
1110
Entry into a VLE page from a non-VLE page
1111
Entry into a non-VLE page from a VLE page
1 _{The device enters Low Power Mode when the Nexus stall mode is enabled}
(Nexus3_DC1[OVC] = 0b011) and a trace message is in danger of over-flowing
the Nexus queue.
Table 36-18 shows the data trace size encodings used for certain messages.
Table 36-18. Data Trace Size Encodings (TCODE = 5, 6, 13, 14)
DTM Size Encoding
Transfer Size
000
001
010
011
100
101–111
Byte
Half-word (2 bytes)
Word (4 bytes)
Double-word (8 bytes)
String (3 bytes)
Reserved
36.6.7 Nexus3+ Memory Map
This section describes the Nexus3+ programmer’s model. Nexus3+ registers are accessed using the
JTAG/OnCE port in compliance with IEEE 1149.1. See Section 36.6.9, Nexus3+ Register Access via
JTAG / OnCE for details on Nexus3+ register access.
NOTE
Nexus3+ registers and output signals are numbered using bit 0 as the least
significant bit. This bit ordering is consistent with the ordering defined by
the IEEE-ISTO 5001 standard.
Table 36-19 details the register map for the Nexus3+ module.
Table 36-19. Nexus3+ Memory Map
Access
Opcode
0x2
0x3
0x4
0x7
0x9
0xA
Register Name
DC1
DC2
DS
RWCS
RWA
RWD
Register Description
Development control 1
Development control 2
Development status
Read/write access control/status
Read/write access address
Read/write access data
Read Address Write Address
0x04
0x06
0x08
0x0E
0x12
0x14
0x05
0x07
—
0x0F
0x13
0x15
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-31