PXN20RM Datasheet, PDF (172/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
Table 7-10. Output Divide Ratios
ERFD
00_0000
00_0001
00_0010
00_0011
00_0100
00_0101
00_0110
00_0111
.
.
.
11_1100
11_1101
11_1110
11_1111
Output Divide Ratio (ERFD+1)
1
2
Invalid
4 (default value for PXN20)
Invalid
6
Invalid
8
.
.
.
Invalid
62
Invalid
64
7.4 Functional Description
The FMPLL module contains the frequency modulated phase lock loop (FMPLL), enhanced frequency
divider (ERFD), enhanced synthesizer control registers (ESYNCR1 and ESYNCR2), synthesizer status
register (SYNSR), and clock/PLL control logic. The block also contains a reference frequency pre-divider
controlled by the EPREDIV bits in the ESYNCR1. This enables the user to use a high frequency crystal
or external clock generator and obtain finer frequency synthesis resolution than would be available if the
raw input clock were used directly by the analog loop. For the remainder of this chapter, the term
“reference frequency” and the symbol F_ref indicate the output of the pre-divider circuit. This is the clock
on which frequency multiplication is performed.
7.4.1 General
At reset, the system clock is driven by the internal oscillator (16 MHz IRC) and the module is in PLL Off
mode. After reset, software can change the PLL mode (see Section 7.5.1, Clock Mode Selection).
Table 7-11 shows the PLL-clock to input-clock frequency relationships for the available clock modes.
Table 7-11. Clock-Out vs. Clock-In Relationships
Clock Mode
Normal PLL Mode
Frequency Equation
F_sys = _---E----P---F--R--^e--E-^x---^t-D-^a---^l_I--^_V---^---E+----M-1----_^F--_--DE-----R-+---F--1--D-6----^-+-----1----_-
7-10
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor