PXN20RM Datasheet, PDF (283/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
10.3.2.7 INTC End-of-Interrupt Register for Processor 1 (Z0) (INTC_EOIR_PRC1)
Offset: INTC_BASE_ADDR + 0x001C
Access: User write-only
0
1
R
2
3
4
5
6
7
8
9
10
11
12
13
14
15
W
INTC_EOIR_PRC1
Reset 0 0
0
0000
0
0
0
0
0
0
0
0
0
16
17
18
19 20 21 22
23
24
25
26
27
28
29
30
31
R
W
INTC_EOIR_PRC1
Reset 0 0
0
0000
0
0
0
0
0
0
0
0
0
Figure 10-15. INTC End-of-Interrupt Register for Processor 1 (Z0) (INTC_EOIR_PRC1)
The register’s function is the same as for processor 0 (Z6) as described in Section 10.3.2.6, INTC
End-of-Interrupt Register for Processor 0 (Z6) (INTC_EOIR_PRC0).
10.3.2.8 INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7)
Offset: INTC_BASE_ADDR + 0x0020
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLR0
CLR1
W
SET0
SET1
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLR2
CLR3
SET2
SET3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-16. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3])
Offset: INTC_BASE_ADDR + 0x0024
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLR4
CLR5
W
SET4
SET5
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLR6
CLR7
SET6
SET7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-17. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7])
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
10-15