PXN20RM Datasheet, PDF (1215/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
– Access Count RWCS[CNT]  0x0000 or 0x0001 (single access)
NOTE
Access Count (CNT) of 0x0000 or 0x0001 performs a single access.
3. The Nexus3+ module then arbitrates for the system bus and the read data is transferred from the
system bus to the RWD register. When the transfer is completed without error (ERR = 0), Nexus
sets the DV bit in the RWCS register. This indicates that the device is ready for the next access.
4. The data can then be read from the read/write access data register (RWD) through the access
method outlined in Section 36.6.9, Nexus3+ Register Access via JTAG / OnCE, using the Nexus
register index of 0xA (see Table 36-19).
NOTE
The DV and ERR bits within the RWCS provide Read/Write Access status
to the external development tool.
36.6.10.6.5 Block Read Access (Non-Burst Mode)
1. For a non-burst block read access, follow Steps 1 and 2 outlined in Section 36.6.10.6.4, Single
Read Access to initialize the registers, but using a value greater than one (0x1) for the CNT field
in the RWCS register.
2. The Nexus3+ module then arbitrates for the system bus and the read data is transferred from the
system bus to the RWD register. When the transfer has completed without error (ERR = 0), the
address from the RWA register is incremented to the next word size (specified in the SZ field) and
the number from the CNT field is decremented.
3. The data can then be read from the read/write access data register (RWD) through the access
method outlined in Section 36.6.9, Nexus3+ Register Access via JTAG / OnCE, using the Nexus
register index of 0xA (see Table 36-19).
4. Repeat steps 3 and 4 in Section 36.6.10.6.4, Single Read Access until the CNT value is zero (0).
When this occurs, the DV bit within the RWCS is set to indicate the end of the block read access.
36.6.10.6.6 Block Read Access (Burst Mode)
1. For a burst block read access, follow Steps 1 and 2 outlined in Section 36.6.10.6.4, Single Read
Access to initialize the registers, using a value of four (double-words) for the CNT field and an
RWCS[SZ] field indicating 64-bit access.
2. The Nexus3+ module then arbitrates for the system bus and the burst read data is transferred from
the system bus to the data buffer (RWD register). For each access within the burst, the address from
the RWA register is incremented to the next double-word (specified in the SZ field) and the number
from the CNT field is decremented.
3. When the entire burst transfer has completed without error (ERR = 0), the DV bit within the RWCS
is set to indicate the end of the block read access.
4. The data can then be read from the burst data buffer (read/write access data register) through the
access method outlined in Section 36.6.9, Nexus3+ Register Access via JTAG / OnCE, using the
Nexus register index of 0xA (see Table 36-19).
5. Repeat step 3 until all double-word values are read from the buffer.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-65